Altera Cyclone V Device Handbook page 486

2-12
Table 2-5: Peripheral Clock Group Clocks
System Clock Name
usb_mp_clk
spi_m_clk
emac0_clk
emac1_clk
l4_mp_clk
l4_sp_clk
can0_clk
can1_clk
gpio_db_clk
h2f_user1_
clock
SDRAM Clock Group
The SDRAM clock group consists of a PLL and clock gating. The clocks in the SDRAM clock group are
derived from the SDRAM PLL. The SDRAM PLL can be programmed to be sourced from the EOSC1 pin,
the EOSC2 pin, or the f2h_sdram_ref_clk clock provided by the FPGA fabric.
Altera Corporation
Frequency
Up to 200 MHz
Up to 240 MHz for the SPI
masters and up to 200 MHz
for the scan manager
Up to 250 MHz
Up to 250 MHz
Up to 100 MHz
Up to 100 MHz
Up to 100 MHz
Up to 100 MHz
Up to 1 MHz
Peripheral PLL C5
Divided From
Peripheral PLL C4
Peripheral PLL C4
Peripheral PLL C0
Peripheral PLL C1
Main PLL C1 or peripheral
PLL C4
Main PLL C1 or peripheral
PLL C4
Peripheral PLL C4
Peripheral PLL C4
Peripheral PLL C4
Peripheral PLL C5
cv_54002
2013.12.30
Constraints and Notes
Clock for USB
Clock for L4 SPI master
bus and scan manager
EMAC0 clock. The
250 MHz clock is
divided internally by the
EMAC into the typical
125/25/2.5 MHz speeds
for 1000/100/10 Mbps
operation.
EMAC1 clock
. The 250 MHz clock is
divided internally by the
EMAC into the typical
125/25/2.5 MHz speeds
for 1000/100/10 Mbps
operation.
Clock for L4 master
peripheral bus
Clock for L4 slave
peripheral bus
Controller area network
(CAN) controller 0
clock
CAN controller 1 clock
Used to debounce
GPIO0, GPIO1, and
GPIO2
Auxiliary user clock to
the FPGA fabric
Clock Manager
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