Altera Cyclone V Device Handbook page 319

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Reset Condition

tx_datak is low, the 8B/10B encoder block encodes the byte at the tx_parallel_data signal as data

(Dx.y). When tx_datak is high, the 8B/10B encoder encodes the input data as a Kx.y code group. The rest

of the tx_parallel_data bytes are encoded as a data word (Dx.y).

Figure 1-26: Control Word and Data Word Transmission

The second 0xBC is encoded as a control word (K28.5).

The IEEE802.3 8B/10B encoder specification identifies only a set of 8-bit characters for which you

must assert tx_datak. If you assert tx_datak for any other set of bytes, the 8B/10B encoder

might encode the output 10-bit code as an invalid code (it does not map to a valid Dx.y or Kx.y code),

or unintended valid Dx.y code, depending on the value entered. It is possible for a downstream

8B/10B decoder to decode an invalid control word into a valid Dx.y code without asserting code

error flags.

Reset Condition

The reset_tx_digital signal resets the 8B/10B encoder. During reset, the running disparity and data

registers are cleared. Also, the 8B/10B encoder outputs a K28.5 pattern from the RD column continuously

until reset_tx_digital is deasserted. The input data and control code from the FPGA fabric is ignored

during the reset state. After reset, the 8B/10B encoder starts with a negative disparity (RD ) and transmits

three K28.5 code groups for synchronization before it starts encoding and transmitting the data on its output.

While reset_tx_digital is asserted, the downstream 8B/10B decoder that receives the data

might observe synchronization or disparity errors.

Encoder Output During Reset Sequence

When in reset (reset_tx_digital is high), a K28.5- (K28.5 10-bit code group from the RD column)

is sent continuously until reset_tx_digital is low. Because of some pipelining of the transmitter

channel PCS, some "don't cares" (10'hxxx) are sent before the three synchronizing K28.5 code groups. User

data follows the third K28.5 code group.

Altera Corporation

tx_datain[7:0]

Transceiver Architecture in Cyclone V Devices

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