Clock Multiplication And Division - Altera Cyclone V Device Handbook

CV-52004
2014.01.10
Related Information
PLL External Clock I/O Pins
Provides more information about PLL clock outputs.

Clock Multiplication and Division

Each Cyclone V PLL provides clock synthesis for PLL output ports using the M/(N × C) scaling factors. The
input clock is divided by a pre-scale factor,
loop drives the VCO to match f
The Quartus II software automatically chooses the appropriate scaling factors according to the input frequency,
multiplication, and division values entered into the ALTERA_PLL megafunction.
VCO Post Divider
A VCO post divider is inserted after the VCO. When you enable the VCO post divider, the VCO post divider
divides the VCO frequency by two. When the VCO post divider is bypassed, the VCO frequency goes to the
output port without being divided by two.
Post-Scale Counter,
Each output port has a unique post-scale counter,
For multiple PLL outputs with different frequencies, the VCO is set to the least common multiple of the
output frequencies that meets its frequency specifications. For example, if the output frequencies required
from one PLL are 33 and 66 MHz, the Quartus II software sets the VCO to 660 MHz (the least common
multiple of 33 and 66 MHz within the VCO range). Then the post-scale counters,
frequency for each output port.
Pre-Scale Counter,
Each PLL has one pre-scale counter,
. The counter does not use duty-cycle control because the only purpose of this counter is to calculate
N N
frequency division. The post-scale counters have a 50% duty cycle setting. The high- and low-count values
for each counter range from 1 to 256. The sum of the high- and low-count values chosen for a design selects
the divide value for a given counter.
Delta-Sigma Modulator
The delta-sigma modulator (DSM) is used together with the
in fractional mode. The DSM dynamically changes the
different
M
Fractional Mode
In fractional mode, the
and the fractional value. The fractional value is equal to
and X = 8, 16, 24, or 32.
Integer Mode
For PLL operating in integer mode,
Clock Networks and PLLs in Cyclone V Devices
Send Feedback
on page 4-23
× (M/N).
in
C
and Multiply Counter,
N
counter values allow the "average"
counter divide value equals to the sum of the "clock high" count, "clock low" count,
M
, and is then multiplied by the
N
, that divides down the output from the VCO post divider.
C
M
, and one multiply counter,
N
M
counter divide value on a cycle to cycle basis. The
M
counter value to be a non-integer.
M
/2^X, where
K
is an integer value and DSM is disabled.
M
Clock Multiplication and Division
feedback factor. The control
M
, scale down the VCO
C
, with a range of 1 to 512 for both
M
multiply counter to enable the PLL to operate
is an integer between 0 and (2^X – 1),
K
4-31
and
M
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