Altera Cyclone V Device Handbook page 492

2-18
Clock Usage By Module
Module Name
Boot ROM
On-chip RAM
DMA controller
FPGA manager
HPS-to-FPGA bridge
FPGA-to-HPS bridge
Lightweight HPS-to-FPGA bridge
Quad SPI flash controller
Altera Corporation
System Clock Name
mpu_l2_ram_clk
osc1_clk
spi_m_clk
l4_sp_clk
l4_mp_clk
l3_main_clk
l3_main_clk
l4_main_clk
dbg_at_clk
l4_mp_clk
cfg_clk
l4_mp_clk
l3_main_clk
l4_mp_clk
l3_main_clk
l4_mp_clk
l4_mp_clk
l4_mp_clk
Use
Clock for the ACP ID mapper
slave and L2 master connections
Clock for the L4 OSC1 bus master
Clock for the L4 SPIM bus master
Clock for the L4 SP bus master
Clock for the quad SPI bus slave
Clock for the boot ROM
Clock for the on-chip RAM
Clock for the DMA
Clock synchronous to the STM
module
Clock synchronous to the quad
SPI flash
Clock for the control block (CB)
data interface and configuration
data slave
Clock for the control slave
Clock for the data slave
Clock for the global programmer's
view (GPV) slave
Clock for the data master
Clock for the GPV slave
Clock for the GPV masters, and
the data and GPV slave
Clock for the control slave
Clock Manager
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cv_54002
2013.12.30