Spi Slave - Altera Cyclone V Device Handbook

cv_54019
19-10

SPI Slave

2013.12.30
by the shift logic when the number of data frames received is equal to the value in the CTRLR1 register plus
one. †
When the handshaking interface on the SPI master is enabled (MHS =1), the status of the target slave is
polled after transmission. Only when the slave reports a ready status does the SPI master complete the transfer
and clear its BUSY status. If the transfer is continuous, the next control/data frame is not sent until the slave
device returns a ready status. †
Related Information
National Semiconductor Microwire Protocol on page 19-14
SPI Slave
The SPI slave handles serial communication with transfer initiated and controlled by serial master peripheral
devices.
• sclk_in serial clock to the SPI slave †
• ss_in_n slave select input to the SPI slave †
• ss_oe_n output enable for the SPI master or slave †
• txd transmit data line for the SPI master or slave †
• rxd receive data line for the SPI master or slave †
When the SPI serial slave is selected, it enables its txd data onto the serial bus. All data transfers to and
from the serial slave are regulated on the serial clock line (sclk_in), driven from the SPI master device.
Data are propagated from the serial slave on one edge of the serial clock line and sampled on the opposite
edge. †
When the SPI serial slave is not selected, it must not interfere with data transfers between the serial-master
and other serial-slave devices. When the serial slave is not selected, its txd output is buffered, resulting in
a high impedance drive onto the SPI master rxd line. The buffers shown in the SPI Slave diagram are external
to SPI controller. spi_oe_n is the SPI slave output enable signal. †
The serial clock that regulates the data transfer is generated by the serial-master device and input to the SPI
slave on sclk_in. The slave remains in an idle state until selected by the bus master. When not actively
transmitting data, the slave must hold its txd line in a high impedance state to avoid interference with serial
transfers to other slave devices. The SPI slave output enable (ss_oe_n) signal is available for use to control
the txd output buffer. The slave continues to transfer data to and from the master device as long as it is
selected. If the master transmits to all serial slaves, a control bit (SLV_OE) in the SPI control register 0
(CTRLR0) can be programmed to inform the slave if it should respond with data from its txd line. †
SPI Controller
Altera Corporation
Send Feedback