Altera Cyclone V Device Handbook page 775

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Table 13-1: Configuration Schemes for FPGA Configuration by the HPS

Configuring the FPGA portion of the SoC device comprises the following phases:

1. Power up phase

2. Reset phase

3. Configuration phase

4. Initialization phase

5. User mode

Related Information

Configuration, Design Security, and Remote System Upgrades

For more information about configuring the FPGA through the HPS, refer to the Configuration, Design

Security, and Remote System Upgrade appendix in the Cyclone V Device Handbook, Volume 1.

Other MSEL values are allowed when the FPGA is configured from a non-HPS source. For information, refer

to the Configuration, DesignSecurity, and Remote System Upgrades in the Cyclone V Device Handbook,

For information about POR delay, refer to the Configuration, Design Security, and Remote System Upgrades

in the Cyclone V Device Handbook, Volume 1.

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