Altera Cyclone V Device Handbook page 293

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Transceiver Banks

Figure 1-5: GX/GT Devices with 12 Transceiver Channels and Two PCIe HIP Blocks

The PCIe HIP blocks are located across Ch 1 and Ch 2 of bank GXB_L0, and Ch 1 and Ch 2 of bank GXB_L2.

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1. 12-channel device transceiver channels are located on

banks L0, L1, L2, and L3.

PCIe Hard IP

PCIe Hard IP

Transceiver Architecture in Cyclone V Devices

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