Altera Cyclone V Device Handbook page 731

cv_54011
2013.12.30
2. Write the block size in bytes to the blksiz register. The controller expects a single/multiple block
transfer.
3. Write to the cmdarg register to indicate the data unit count.
Register Settings for ATA Payload Transfer
You must set the cmdarg, cmd, blksiz, and bytcnt registers according to the following tables.
Table 11-27: cmdarg Register Settings for ATA Payload Transfer
Bits
31
30:24
23:16
15:8
7:0
Table 11-28: cmd Register Settings for ATA Payload Transfer
Bits
start_cmd
ccs_expected
read_ceata_device
update_clk_regs_only
card_num
send_initialization
stop_abort_cmd
send_auto_stop
transfer_mode
read_write
data_expected
response_length
response_expect
SD/MMC Controller
Send Feedback
†
Value
1 or 0
0
0
Data count
Data count
1
1
0 or 1
0
0
0
0
0
0
1 or 0
1
0
1
Register Settings for ATA Payload Transfer
†
Set to 0 for read operation or set to 1 for write operation
Reserved (bits set to 0 by host processor)
Reserved (bits set to 0 by host processor)
Data Count Unit [15:8]
Data Count Unit [7:0]
†
Value
CCS is expected. Set to 1 for the RW_BLK command
if interrupts are enabled in CE-ATA card device
(the nIEN bit is set to 0 in the ATA control register)
Set to 1 for a RW_BLK or RW_REG read command
No clock parameters update command
No initialization sequence
Block transfer mode. Byte count must be integer
multiple of 4kB. Block size can be 512, 1k or 4k bytes
1 for write and 0 for read
Data is expected
†
Comment
Comment
-
-
-
-
-
-
11-53
†
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