Clocks; Resets - Altera Cyclone V Device Handbook

cv_54015
2013.12.30
Table 15-3: JTAP-AP Byte Command Protocol
Bits of the
Command Byte
7 6
0 Opcode
Payload
1 0
1 0
1 1
1 1
Related Information
• Scan Manager Address Map and Register Definitions
• Info center
For details about the byte command protocol, refer to the JTAG-AP chapter in the ARM Debug Interface
v5 Architecture Specification, which you can download from the ARM info center website.

Clocks

The scan manager is connected to the spi_m_clk clock generated by the clock manager.
The scan manager generates two clocks. One clock routes to the control block of the FPGA portion of the
SoC device with a frequency of spi_m_clk / 6 and runs at a maximum of 33 MHz. The other clock routes
to the HPS I/O scan chains with a frequency of sp i_m_clk / 2 and runs at a maximum frequency of
100 MHz.
Note:
The spi_m_clk can potentially run faster than the scan manager supports so that SPI masters can
support 60 Mbps rates. When the SPI master is running faster than what is supported by the scan
manager, the scan manager cannot be used and must be held in reset.
Related Information
Clock Manager
For more information, including minimum and maximum clock frequencies, refer to the Clock Manager
chapter.

Resets

The reset manager provides the scan_manager_rst_n reset signal to the scan manager for both cold
and warm resets.
Because glitches can happen on the output clocks during a warm reset, the scan manager temporarily stops
generation of the JTAG-AP and I/O configuration clocks. This action ensures that a warm reset does not
cause output clock glitches.
Scan Manager
Send Feedback
5 4
0 Opcode
Payload
1 X
0 X
1 X
on page 2-1
3 2 1
X X X
X X X
X X X
on page 15-8
15-7
Clocks
Opcode
0
TMS
TDI_TDO
X Reserved
X Reserved
X Reserved
Altera Corporation