Altera Cyclone V Device Handbook page 337

1-50
Document Revision History
Table 1-30: Document Revision History
Date
May 2013
Altera Corporation
Version
• Updated the 6.144 Gbps CPRI Support Capability in GT
Devices section.
2013.05.06 • Added link to the known document issues in the
Knowledge Base
• Updated the Transceiver Architecture in Cyclone V
Devices section.
• Updated the Architecture Overview section.
• Updated the Automatic Lock Mode section.
• Updated the Transmitter Buffer section.
• Updated Table 1-2.
• Updated Table 1-5.
• Updated the Rate Match FIFO section.
• Updated the Transceiver Banks section.
• Added the Channel Variants section.
• Updated the Transceiver Channel Architecture section.
• Updated Figure 1-7.
• Updated the Transmitter PLL section.
• Updated the Channel PLL Architecture section.
• Updated the Channel PLL as CDR PLL section.
• Updated the CDR PLL in Automatic Lock Mode section.
• Added the CDR PLL in Manual Lock Mode section.
• Updated the Channel PLL as a CMU PLL section.
• Added the fPLL as a Transmitter PLL section.
• Updated the Clock Divider section.
• Updated the Receiver PMA Datapath section.
• Updated the Receiver Buffer section.
• Updated the Programmable Receiver V
• Updated the Transmitter PMA Datapath section.
• Added the Bit Reversal section.
• Updated the Transmitter Buffer section.
• Updated the Transmitter Buffer Features and Capabili-
ties section.
• Updated the Transmitter Protocol Specific section.
• Updated the Calibration Block section.
• Updated the PCS Architecture section.
• Updated the Transmitter Phase Compensation FIFO
section.
• Added the Registered Mode section.
• Updated the Byte Serializer section.
• Updated the 8B/10B Encoder in Single-Width Mode
section.
Changes
CM
Transceiver Architecture in Cyclone V Devices
CV-53001
2013.05.06
section.
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