Altera Cyclone V Device Handbook page 403

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2013.10.17
Synchronization
The word aligner block in the receiver PCS of each of the four XAUI lanes implements the receiver
synchronization state diagram shown in Figure 48-7 of the IEEE802.3-2008 specification.
The XAUI PHY IP core provides a status signal per lane to indicate if the word aligner is synchronized to a
valid word boundary.
Deskew
The lane aligner block in the receiver PCS implements the receiver deskew state diagram shown in Figure
48-8 of the IEEE 802.3-2008 specification.
The lane aligner starts the deskew process only after the word aligner block in each of the four XAUI lanes
indicates successful synchronization to a valid word boundary.
The XAUI PHY IP core provides a status signal to indicate successful lane deskew in the receiver PCS.
Clock Compensation
The rate match FIFO in the receiver PCS datapath compensates up to ±100 ppm difference between the
remote transmitter and the local receiver. It does so by inserting and deleting Skip ||R|| columns, depending
on the ppm difference.
The clock compensation operation begins after:
• The word aligner in all four XAUI lanes indicates successful synchronization to a valid word boundary.
• The lane aligner indicates a successful lane deskew.
The rate match FIFO provides status signals to indicate the insertion and deletion of the Skip ||R|| column
for clock rate compensation.
Transceiver Protocol Configurations in Cyclone V Devices
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XAUI Supported Features
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