Internal Clocking - Altera Cyclone V Device Handbook

CV-53002
2013.05.06

Internal Clocking

This section describes the clocking architecture internal to Cyclone V transceivers.
Different physical coding sublayer (PCS) configurations and channel bonding options result in various
transceiver clock paths.
Note: The Quartus II software automatically performs the internal clock routing based on the transceiver
configuration that you select.
The labels listed in the following table and figure mark the three sections of the transceiver internal clocking.
Table 2-2: Internal Clocking Subsections
Label
A Transmitter Clock Network
B Transmitter Clocking
C Receiver Clocking
Figure 2-5: Internal Clocking
Transmit
PLL
Clock Lines
×1 ×6
Transmitter Clock Network
The transmitter PLL is comprised of the CMU PLL. All CMU PLLs are identical, but the usage varies
depending on channel location due to the availability of access to the clock distribution network.
Transceiver Clocking in Cyclone V Devices
Send Feedback
Scope
Transmitter
Clock
Network
A
Transceiver Channel
Transmitter
Receiver
Transceiver Channel
Transmitter
×N
Receiver
Clock distribution from transmitter PLLs to channels
Clocking architecture within transmitter channel datapath
Clocking architecture within receiver channel datapath
B
tx_serial_data
CDR
C
rx_serial_data
Input
Reference Clock
tx_serial_data
CDR
rx_serial_data
Input
Reference Clock
Internal Clocking
Description
Altera Corporation
2-5