Transceiver Reset Control Signals Using Avalon Memory Map Registers - Altera Cyclone V Device Handbook

CV-53003
2013.05.06
Figure 3-8: Reset Sequence Timing Diagram for Receiver using the User-Coded Reset Controller
during Device Operation
Related Information
Transceiver Architecture in Cyclone V Devices
For information about CDR lock modes.
Transceiver Reset Using Avalon Memory Map Registers
You can use Memory Map registers within the PHY IP instance to control the reset signals through the
Avalon Memory Map interface.
This gives the flexibility of resetting the PLL, and transmitter and receiver analog and digital blocks separately
without repeating the entire reset sequence.

Transceiver Reset Control Signals Using Avalon Memory Map Registers

The following table lists the memory map registers for CDR lock mode and channel reset. These signals
help you reset your transceiver when you use Memory Map registers within the PHY IP.
Table 3-4: Transceiver Reset Control Using Memory Map Registers
Register Name
pma_rx_set_locktodata
pma_rx_set_locktoref
Transceiver Reset Control in Cyclone V Devices
Send Feedback
mgmt_rst_reset
rx_analogreset 1
1
rx_digitalreset
rx_is_lockedtodata
rx_cal_busy
Transceiver Reset Using Avalon Memory Map Registers
2
t two clock cycles of user control reset
rx_analogreset
3
This register is for CDR manual lock mode only. When you set
the register to high, the RX CDR PLL is in the lock to data (LTD)
mode. The default is low when both registers have the CDR in
auto lock mode.
This register is for CDR manual lock mode only. When you set
the register to high, the RX CDR PLL is in the lock to reference
(LTR) mode if pma_rx_set_lockedtodata is not asserted.
The default is low when both registers have the CDR in auto
lock mode.
4
t
LTD
Description
3-11
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