Guideline: Use The Same V; Ccpd For All I/O Banks In A Group - Altera Cyclone V Device Handbook

CV-52005
2014.01.10
Figure 5-4: Phase Relationship for External PLL Interface Signals
VCO clk
(internal PLL clk)
(-180° phase shift)
(288° phase shift)
(-18° phase shift)
RX serial data
tx_outclk
TX serial data
Connection between Altera_PLL and ALTLVDS
Figure 5-5: LVDS Interface with the Altera_PLL Megafunction
This figure shows the connections between the Altera_PLL and ALTLVDS megafunction.
When generating the Altera_PLL megafunction, the Left/Right PLL option is configured to set up the PLL
in LVDS mode. Instantiation of

Guideline: Use the Same V

In the Cyclone V devices, all I/O banks have individual V
share V
CCPD
Banks 1A (if available) and 2A
Banks 3B and 4A
Banks 7A and 8A
I/O Features in Cyclone V Devices
Send Feedback
inclk0
outclk0
outclk1
outclk2
D1 D2
D1 D2
FPGA Fabric
Transmitter
Core Logic
tx_coreclk
rx_coreclk
Receiver
Core Logic
pll_areset
for All I/O Banks in a Group
CCPD
in each group:
Connection between Altera_PLL and ALTLVDS
D3 D4 D5 D6
D3 D4 D5 D6
LVDS Transmitter
(ALTLVDS)
D Q
tx_in tx_inclock
tx_enable
LVDS Receiver
(ALTLVDS)
Q D
rx_inclock
rx_out
rx_enable
pll_areset
is optional.
CCPD
D7 D8 D9
D7 D8 D9 D10
Altera_PLL
outclk0
outclk1
outclk2
inclk0
pll_areset
locked
except the following I/O bank groups, which
5-17
D10
Altera Corporation