Altera Cyclone V Device Handbook page 560

6-14
GIC Interrupt Map for the Cyclone V SoC HPS
GIC Source Block
Interrupt
Number
(6)
67 L2-Cache
68 L2-Cache
69 L2-Cache
70 L2-Cache
71 DDR
72 FPGA
73 FPGA
74 FPGA
75 FPGA
76 FPGA
77 FPGA
78 FPGA
79 FPGA
80 FPGA
81 FPGA
82 FPGA
83 FPGA
84 FPGA
85 FPGA
86 FPGA
87 FPGA
88 FPGA
(6)
To ensure that you are using the correct GIC interrupt number, your code should refer to the symbolic interrupt
name, as shown in the Interrupt Name column. Symbolic interrupt names are defined in a header file distributed
with the source installation for your operating system.
(9)
This interrupt combines the following interrupts: DECERRINTR, ECNTRINTR, ERRRDINTR, ERRRTINTR,
ERRWDINTR, ERRWTINTR, PARRDINTR, PARRTINTR, and SLVERRINTR
Altera Corporation
Interrupt Name
l2_ecc_byte_wr_IRQ
l2_ecc_corrected_IRQ
l2_ecc_uncorrected_IRQ
l2_combined_IRQ
ddr_ecc_error_IRQ
FPGA_IRQ0
FPGA_IRQ1
FPGA_IRQ2
FPGA_IRQ3
FPGA_IRQ4
FPGA_IRQ5
FPGA_IRQ6
FPGA_IRQ7
FPGA_IRQ8
FPGA_IRQ9
FPGA_IRQ10
FPGA_IRQ11
FPGA_IRQ12
FPGA_IRQ13
FPGA_IRQ14
FPGA_IRQ15
FPGA_IRQ16
Combined Triggering
Interrupts
Edge
Edge
Edge
(9)
Level
Level
Level or Edge
Level or Edge
Level or Edge
Level or Edge
Level or Edge
Level or Edge
Level or Edge
Level or Edge
Level or Edge
Level or Edge
Level or Edge
Level or Edge
Level or Edge
Level or Edge
Level or Edge
Level or Edge
Level or Edge
Cortex-A9 Microprocessor Unit Subsystem
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2013.12.30