Altera Cyclone V Device Handbook page 61

4-4
Regional Clock Networks
Figure 4-1: GCLK Networks in Cyclone V E, GX, and GT Devices
This figure represents the top view of the silicon die that corresponds to a reverse view of the device package.
Figure 4-2: GCLK Networks in Cyclone V SE, SX, and ST Devices
This figure represents the top view of the silicon die that corresponds to a reverse view of the device package.
Regional Clock Networks
RCLK networks are only applicable to the quadrant they drive into. RCLK networks provide the lowest clock
insertion delay and skew for logic contained within a single device quadrant. The Cyclone V IOEs and
Altera Corporation
CLK[8..11][p,n]
GCLK[12..15]
GCLK[0..3]
Q1 Q2
Q4 Q3
GCLK[4..7]
CLK[0..3][p,n]
CLK[6,7][p,n]
GCLK[12..15]
GCLK[0..3]
Q1 Q2
Q4 Q3
GCLK[4..7]
CLK[0..3][p,n]
GCLK[8..11]
For Cyclone V E A2 and A4
devices, and Cyclone V GX C3
device, only CLK[6][p,n] pins are
available.
GCLK[8..11]
GCLK network is not available in
quadrant 2 for Cyclone V SE A5 and
A6 devices, Cyclone V ST D5 and
D6 devices, and Cyclone V SX C5
and C6 devices.
Clock Networks and PLLs in Cyclone V Devices
CV-52004
2014.01.10
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