Configuring The Flash Device - Altera Cyclone V Device Handbook

cv_54012
2013.12.30
For example, to perform a basic read of four bytes to a flash device that has three address bytes, software
must write a total of eight bytes to the TX FIFO buffer. The first byte would be the instruction opcode, the
next three bytes are the address, and the final four bytes would be dummy data to ensure the chip select stays
active while the read data is returned. Similarly, because eight bytes were written to the TX FIFO buffer,
software should expect eight bytes to be returned in the RX FIFO buffer. The first four bytes of this would
be discarded, leaving the final four bytes holding the data read from the device.
Because the TX FIFO and RX FIFO buffers are four bytes deep each, software must maintain the FIFO buffer
levels to ensure the TX FIFO buffer does not underflow and the RX FIFO buffer does not overflow. Interrupts
are provided to indicate when the fill levels pass the watermark levels, which are configurable through the
TX threshold register (txtresh) and RX threshold register (rxtresh).

Configuring the Flash Device

For read and write accesses, software must initialize the device read instruction register (devrd) and the
device write instruction register (devwr). These registers include fields to initialize the instruction opcodes
that should be used as well as the instruction type, and whether the instruction uses single, dual or quad pins
for address and data transfer. To ensure the quad SPI controller can operate from a reset state, the opcode
registers reset to opcodes compatible with single I/O flash devices.
The quad SPI flash controller uses the instruction transfer width field (instwidth) of the devrd register
to set the instruction transfer width for both reads and writes. There is no instwidth field in the devwr
register. If instruction type is set to dual or quad mode, the address transfer width (addrwidth) and data
transfer width (datawidth) fields of both registers are redundant because the address and data type is
based on the instruction type. Thus, software can support the less common flash instructions where the
opcode, address, and data are sent on two or four lanes. For most instructions, the opcodes are sent serially
to the flash device, even for dual and quad instructions. One of the flash devices that supports instructions
that can send the opcode over two or four lanes is the Micron N25Q128. For reference,
12-2 show how software should configure the quad SPI controller for each specific read and write instruction,
respectively, supported by the Micron N25Q128 device.
Table 12-1: Quad SPI Configuration for Micron N25Q128 Device (Read Instructions)
Instruction Lanes Used By
Read 1
Fast read 1
Dual 1
output fast
read
(DOFR)
Dual I/O 1
fast read
(DIOFR)
Quad 1
output fast
read
(QOFR)
Quad I/O 1
fast read
(QIOFR)
Quad SPI Flash Controller
Send Feedback
Lanes Used to
Opcode Send Address
1
1
1
2
1
4
Lanes Used to instwidth Value
Send Data
1 0
1 0
2 0
2 0
4 0
4 0
Configuring the Flash Device
Table 12-1
addrwidth datawidth
Value
0 0
0 0
0 1
1 1
0 2
2 2
Altera Corporation
12-9
and Table
Value