Initializing Mac - Altera Cyclone V Device Handbook

cv_54017
2013.12.30
• Receive and Transmit Store And Forward
• Receive and Transmit Threshold Control (RTC and TTC)
• Hardware Flow Control enable
• Flow Control Activation and De-activation thresholds for MTL Receive and Transmit FIFO buffers
(RFA and RFD)
• Error frame and undersized good frame forwarding enable
• OSF Mode
10. Clear the interrupt requests, by writing to those bits of the status register (interrupt bits only) that are
set. For example, by writing 1 into bit 16, the normal interrupt summary clears this bit (DMA Register
5 (Status Register)).
11. Enable the interrupts by programming the Register 7 (Interrupt Enable Register).
Note:
12. Read Register 11 (AHB or AXI Status) to confirm that all previous transactions are complete.
Note:
13. Start the receive and transmit DMA by setting SR (bit 1) and ST (bit 13) of the control register (DMA
Register 6 (Operation Mode Register).
Related Information
Descriptors
Detailed bit map of the descriptor structure

Initializing MAC

The following MAC Initialization operations can be performed after DMA initialization. If the MAC
initialization is done before the DMA is set-up, then enable the MAC receiver (last step below) only after
the DMA is active. Otherwise, received frames fill the RX FIFO buffer and overflow.
1. Program the EMAC Register 4 (GMII Address Register) for controlling the management cycles for
external PHY. For example, Physical Layer Address PA (bits 15-11). In addition, set bit 0 (GMII Busy)
for writing into PHY and reading from PHY. †
2. Read the 16-bit data of Register 5 (GMII Data Register) from the PHY for link up, speed of operation,
and mode of operation, by specifying the appropriate address value in bits 15-11 of Register 4 (GMII
Address Register). †
3. Provide the MAC address registers (Register 16 (MAC Address0 High Register) and Register 17 (MAC
Address0 Low Register)). Because 128 MAC addresses are supported, you need to program the MAC
addresses accordingly.
4. Program Register 2 (Hash Table High Register) and Register 3 (Hash Table Low Register).
5. Program the following fields to set the appropriate filters for the incoming frames in Register 1 (MAC
Frame Filter): †
• Receive All †
• Promiscuous mode †
• Hash or Perfect Filter †
• Unicast, multicast, broadcast, and control frames filter settings †
6. Program the following fields for proper flow control in Register 6 (Flow Control Register): †
Ethernet Media Access Controller
Send Feedback
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Perform 12 on page 1-53 only if you did not perform
If any previous transaction is still in progress when you read the Register 11 (AHB or AXI Status),
then it is strongly recommended to check the slave components addressed by the master interface.
on page 17-36
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Initializing MAC
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3 on page 1-52.
17-53
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