Resetting The Transceiver With The Phy Ip Embedded Reset Controller During Device Power-Up - Altera Cyclone V Device Handbook

CV-53003
2013.05.06
Signal Name
reconfig_busy
pll_locked
rx_is_lockedtodata
rx_is_lockedtoref
mgmt_clk_clk
mgmt_rst_reset
Resetting the Transceiver with the PHY IP Embedded Reset Controller during Device
Power-Up
Follow this reset sequence to ensure a reliable link initialization after the initial power-up.
The numbers in the following figure correspond to the following numbered list, which guides you through
the transceiver reset sequence during device power-up.
1. During device power-up, mgmt_rst_reset and phy_mgmt_clk_reset must be asserted to
initialize the reset sequence. phy_mgmt_clk_reset holds the transceiver blocks in reset and
mgmt_rst_reset is required to start the calibration IPs. Both these signals should be held asserted
for a minimum of two phy_mgmt_clk clock cycles. Deassert phy_mgmt_clk_reset at the same
time as mgmt_rst_reset.
2. After the transmitter calibration and reset sequence are complete, the tx_ready status signal is asserted
and remains asserted to indicate that the transmitter is ready to transmit data.
Transceiver Reset Control in Cyclone V Devices
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Resetting the Transceiver with the PHY IP Embedded Reset Controller during Device Power-Up

Signal
Status Output
Status Output
Status Output
Status Output
Clock
Reset
Description
An output from the Transceiver Reconfiguration
Controller block indicates the status of the dynamic
reconfiguration controller. At the first mgmt_clk_
clk clock cycle after power-up, reconfig_busy
remains low.
This signal is asserted from the second mgmt_clk_
clk clock cycle to indicate that the calibration process
is in progress . When the calibration process is
completed, the reconfig_busy signal is deasserted.
This signal is also routed to the embedded reset
controller by the Quartus
the signal in the reconfig_to_xcvr bus between
the PHY IP and the Transceiver Reconfiguration
Controller.
This signal is asserted when the TX PLL achieves lock
to the input reference clock. When this signal is
asserted high, the embedded reset controller deasserts
the tx_digitalreset signal.
This signal is an optional output status port. When
asserted, this signal indicates that the CDR is locked
to the RX data and the CDR has changed from lock-
to-reference (LTR) to lock-to-data (LTD) mode.
This is an optional output status port. When asserted,
this signal indicates that the CDR is locked to the
reference clock.
Clock for the Transceiver Reconfiguration Controller.
This clock must be stable before releasing mgmt_
rst_reset.
Reset for the Transceiver Reconfiguration Controller
®
II software by embedding
Altera Corporation
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