Altera Cyclone V Device Handbook page 693

cv_54011
2013.12.30
• Load card command parameters
• Send commands to card bus
• Receive responses from card bus
• Send responses to BIU
• Load clock parameters
• Drives the P-bit on command pin
A new command is issued to the controller by writing to the BIU registers and setting the start_cmd bit
in the cmd register. The command path loads the new command (command, command argument, timeout)
and sends an acknowledgement to the BIU.
After the new command is loaded, the command path state machine sends a command to the card
bus including the internally generated seven-term CRC (CRC-7) and receives a response, if any. The
state machine then sends the received response and signals to the BIU that the command is done, and then
waits for eight clock cycles before loading a new command. In CE-ATA data payload transfer
(RW_MULTIPLE_BLOCK) commands, if the card device interrupts are enabled (the nIEN bit is set to 0 in
the ATA control register), the state machine performs the following actions after receiving the response:
• Does not drive the P-bit; it waits for CCS, decodes and goes back to idle state, and then drives the P-bit.
• If the host wants to send the CCSD command and if eight clock cycles are expired after the response, it
sends the CCSD pattern on the command pin.
Load Command Parameters
Commands or responses are loaded in the command path in the following situations:
• New command from BIU When the BIU sends a new command to the CIU, the start_cmd bit is set
to 1 in the cmd register.
• Internally-generated send_auto_stop When the data path ends, the SD/SDIO STOP command
request is loaded.
• Interrupt request (IRQ) response with relative card address (RCA) 0x000 When the command path is
waiting for an IRQ response from the MMC and a "send irq response" request is signaled by the BIU,
the send IRQ request bit (send_irq_response) is set to 1 in the ctrl register.
Loading a new command from the BIU in the command path depends on the following cmd register bit
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settings:
• update_clock_registers_only If this bit is set to 1 in the cmd register, the command path
updates only the clkena, clkdiv, and clksrc registers. If this bit is set to 0, the command path loads
the cmd, cmdarg, and tmout registers. It then processes the new command, which is sent to the card.
• wait_prvdata_complete If this bit is set to 1, the command path loads the new command under
one of the following conditions:
• Immediately, if the data path is free (that is, there is no data transfer in progress), or if an open-ended
data transfer is in progress (bytcnt = 0).
• After completion of the current data transfer, if a predefined data transfer is in progress.
Send Command and Receive Response
After a new command is loaded in the command path (the update_clock_registers_only bit in
the cmd register is set to 0), the command path state machine sends out a command on the card bus.
SD/MMC Controller
Send Feedback
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Load Command Parameters
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