User-Coded Reset Controller - Altera Cyclone V Device Handbook

CV-53003
2013.05.06
Figure 3-3: Reset Sequence Timing Diagram Using Embedded Reset Controller during Device
Operation
Note: To reset the transmitter and receiver analog and digital blocks separately without
repeating the entire reset sequence, use the Avalon Memory Map registers.

User-Coded Reset Controller

You must implement external reset controller logic (user-coded reset controller) if you disable the embedded
reset controller to initialize the transceiver physical coding sublayer (PCS) and physical medium attachment
(PMA) blocks.
You can implement a user-coded reset controller with one of the following:
• Using your own Verilog/VHDL code to implement the reset sequence
• Using the Quartus II MegaWizard Plug-In Manager, which provides a ready-made reset controller IP to
place your own verilog/vhdl code
Note: You must disable the embedded reset controller before using the user-coded reset controller.
Note: The embedded reset controller can only be disabled for non-protocol transceiver PHY IPs, such as
custom PHY, low latency PHY and deterministic latency PHY. Native PHY IP does not have an
embedded reset controller, so you must implement your own reset logic.
If you implement your own reset controller, consider the following:
• The user-coded reset controller must be level sensitive (active high)
• The user-coded reset controller does not depend on phy_mgmt_clk_reset
• You must provide a clock and reset to the reset controller logic
• The internal signals of the PHY IP embedded reset controller are configured as ports
• You can hold the transceiver channels in reset by asserting the appropriate reset control signals
Transceiver Reset Control in Cyclone V Devices
Send Feedback
Control Signals
1
phy_mgmt_clk_reset
tx_ready
rx_ready
Status Signals
reconfig_busy
pll_locked
rx_is_lockedtodata
User-Coded Reset Controller
2
3
3-5
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