Watchdog Timer Block Diagram And System Integration; Functional Description Of The Watchdog Timer; Watchdog Timer Counter - Altera Cyclone V Device Handbook

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Watchdog Timer Block Diagram and System Integration

Watchdog Timer Block Diagram and System Integration
Each watchdog timer consists of a slave interface for control and status register (CSR) access, a register block,
and a 32-bit down counter that operates on the slave interface clock (osc1_clk). A pause input, driven
by the system manager, optionally pauses the counter when a CPU is being debugged.
The watchdog timer drives an interrupt request to the MPU and a reset request to the reset manager.
Figure 24-1: Watchdog Timer Block Diagram
Related Information
• Reset Manager
For more information, refer to the Reset Manager chapter.
• Cortex-A9 MPCore
For more information about the watchdog timers in the MPU, refer to Cortex A9 Microprocessor Unit
Subsystem.

Functional Description of the Watchdog Timer

Watchdog Timer Counter

Each watchdog timer is a programmable, little-endian down counter that decrements by one on each clock
cycle. The watchdog timer supports 16 fixed timeout period values and software chooses which timeout
periods are desired. A timeout period is 2n osc1_clk clock periods, where n is an integer from 16 to 31
inclusive.
If the counter reaches zero, the watchdog timer has timed out, indicating an unrecoverable error has occurred
and a system reset is needed. Software must continually restart the timer (which reloads the counter with
the restart timeout period value) to indicate that the system is functioning normally. Software can reload
the counter at any time by writing to the restart register.
Software sets the watchdog timer output response mode to either generate a reset request on a timeout, or
assert an interrupt request and start counting down a second time. In the former case, the counter wraps
and keeps decrementing, even while a reset request is asserted, until the watchdog timer is reset by the reset
manager. In the latter case, the generated interrupt is passed to the generic interrupt controller (GIC) in the
Altera Corporation
System
Pause
Manager
L4 Peripheral Bus (osc1_clk)
on page 3-1
on page 6-4
Watchdog Timer
Reset
Request
Interrupt &
System Reset
Control Interrupt
Register Block
Slave Interface
Reset
Manager
MPU
Watchdog Timer
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2013.12.30