Altera Cyclone V Device Handbook page 712

11-34
Clock Setup
The following list shows typical clock frequencies for various types of cards:
• SD memory card, 25 MHz
• MMC card device, 12.5 MHz
• Full speed SDIO, 25 MHz
• Low speed SDIO, 400 kHz
Related Information
www.sdcard.org
To learn more about how SD technology works, visit the SD Association website.
Clock Setup
The following registers of the SD/MMC controller allow software to select the desired clock frequency for
the card:
• clksrc
• clkdiv
• clkena
The controller loads these registers when it receives an update clocks command.
Changing the Card Clock Frequency
To change the card clock frequency, perform the following steps:
1. Before disabling the clocks, ensure that the card is not busy with any previous data command. To do so,
verify that the data_busy bit of the status register (status) is 0.
2. Reset the cclk_enable bit of the clkena register to 0, to disable the card clock generation.
3. Reset the clksrc register to 0.
4. Set the following bits in the cmd register to 1:
• update_clk_regs_only Specifies the update clocks command
• wait_prvdata_complete Ensures that clock parameters do not change until any ongoing data
transfer is complete
• start_cmd Initiates the command
5. Wait until the start_cmd and update_clk_regs_only bits change to 0. There is no interrupt
when the clock modification completes. The controller does not set the command_done bit in the
rintsts register upon command completion. The controller might signal a hardware lock error if it
already has another command in the queue. In this case, return to
For information about hardware lock errors, refer to Interrupt and Error Handling.
6. Reset the sdmmc_clk_enable bit to 0 in the enable register of the clock manager peripheral PLL
group (perpllgrp).
7. In the control register (ctrl) of the SDMMC controller group (sdmmcgrp) in the system manager,
set the drive clock phase shift select (drvsel) and sample clock phase shift select (smplsel) bits to
specify the required phase shift value.
8. Set the sdmmc_clk_enable bit in the Enable register of the clock manager perpllgrp group to
1.
9. Set the clkdiv register of the controller to the correct divider value for the required clock frequency.
10. Set the cclk_enable bit of the clkena register to 1, to enable the card clock generation.
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Step 4.
SD/MMC Controller
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2013.12.30