Clock Output Connections; Clock Control Block - Altera Cyclone V Device Handbook

CV-52004
2014.01.10
RCLK[52,53,54,55,56,57,72,78]
RCLK[52,53,54,55,56,57,73,79]
RCLK[0,4,8,10,14,18,40,41,42,43,44,45,64,68,82,86]
RCLK[1,5,9,11,15,19,40,41,42,43,44,45,65,69,83,87]
RCLK[2,6,12,16,40,41,42,43,44,45,46,47,48,49,50,51,66,84]
RCLK[3,7,13,17,40,41,42,43,44,45,46,47,48,49,50,51,67,85]
Table 4-5: Dedicated Clock Input Pin Connectivity to the RCLK Networks for Cyclone V SE, SX, and ST Devices
A given clock input pin can drive two adjacent RCLK networks to create a dual-regional clock network.
RCLK[20,24,28,30,34,38,58,59,60,61,62,63,64,68,82,86]
RCLK[21,25,29,31,35,39,58,59,60,61,62,63,65,69,83,87]
RCLK[22,26,32,36,52,53,54,55,56,57,58,59,60,61,62,63,66,84]
RCLK[23,27,33,37,52,53,54,55,56,57,58,59,60,61,62,63,67,85]
RCLK[52,53,54,55,56,57,78]
RCLK[52,53,54,55,56,57,79]
RCLK[0,4,8,40,41,42,43,44,45,64,68,82,86]
RCLK[1,5,9,40,41,42,43,44,45,65,69,83,87]

Clock Output Connections

For Cyclone V PLL connectivity to GCLK and RCLK networks, refer to the PLL connectivity to GCLK and
RCLK networks spreadsheet.
Related Information
PLL Connectivity to GCLK and RCLK Networks for Cyclone V Devices

Clock Control Block

Every GCLK, RCLK, and PCLK network has its own clock control block. The control block provides the
following features:
Clock source selection (dynamic selection available only for GCLKs)
Global clock multiplexing
Clock power down (static or dynamic clock enable or disable available only for GCLKs and RCLKs)
Clock Networks and PLLs in Cyclone V Devices
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Clock Resources
Clock Resources
Clock Output Connections
CLK (p/n Pins)
CLK[6]
(4)
CLK[7]
CLK[8]
CLK[9]
CLK[10]
CLK[11]
CLK (p/n pins)
CLK[0]
CLK[1]
CLK[2]
CLK[3]
(3)
CLK[4]
(3)
CLK[5]
CLK[6]
CLK[7]
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