Lvds Interface With External Pll Mode - Altera Cyclone V Device Handbook

CV-52005
2014.01.10

LVDS Interface with External PLL Mode

The MegaWizard Plug-In Manager provides an option for implementing the LVDS interface with the Use
External PLL option. With this option enabled you can control the PLL settings, such as dynamically
reconfiguring the PLL to support different data rates, dynamic phase shift, and other settings. You must also
instantiate the an Altera_PLL megafunction to generate the various clock and load enable signals.
If you enable the Use External PLL option with the ALTLVDS transmitter and receiver, the following signals
are required from the Altera_PLL megafunction:
Serial clock input to the SERDES of the ALTLVDS transmitter and receiver
Load enable to the SERDES of the ALTLVDS transmitter and receiver
Parallel clock used to clock the transmitter FPGA fabric logic and parallel clock used for the receiver
rx_syncclock
Asynchronous PLL reset port of the ALTLVDS receiver
Altera_PLL Signal Interface with ALTLVDS Megafunction
Table 5-12: Signal Interface Between Altera_PLL and ALTLVDS Megafunctions
This table lists the signal interface between the output ports of the Altera_PLL megafunction and the input ports of
the ALTLVDS transmitter and receiver. As an example, the table lists the serial clock output, load enable output,
and parallel clock output generated on ports outclk0, outclk1, and outclk2, along with the locked signal of the
Altera_PLL instance. You can choose any of the PLL output clock ports to generate the interface clocks.
From the Altera_PLL Megafunction
Serial clock output (outclk0)
The serial clock output (outclk0) can
only drive
tx_inclock
ALTLVDS transmitter, and
on the ALTLVDS receiver.
inclock
This clock cannot drive the core logic.
Load enable output (outclk1)
Parallel clock output (outclk2)
~(locked)
Note: With soft SERDES, a different clocking requirement is needed.
I/O Features in Cyclone V Devices
Send Feedback
port and receiver FPGA fabric logic
To the ALTLVDS Transmitter
tx_inclock
input to the transmitter)
on the
rx_
tx_enable
the transmitter)
Parallel clock used inside
the transmitter core logic in
the FPGA fabric
LVDS Interface with External PLL Mode
(serial clock
rx_inclock
(load enable to
rx_enable
deserializer)
parallel clock used inside the receiver
core logic in the FPGA fabric
—
pll_areset
port)
The
pll_areset
enabled for the LVDS receiver in
external PLL mode. This signal does
not exist for LVDS transmitter
instantiation when the external PLL
option is enabled.
To the ALTLVDS Receiver
(serial clock input)
(load enable for the
(asynchronous PLL reset
signal is automatically
Altera Corporation
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