Altera Cyclone V Device Handbook page 70

CV-52004
2014.01.10
Figure 4-10: RCLK Control Block for Cyclone V Devices
You can set the input clock sources and the
through the Quartus II software using the ALTCLKCTRL megafunction.
Note: When selecting the clock source dynamically using the ALTCLKCTRL megafunction, choose the
inputs using the
ports of the multiplexer, and the PLL outputs feed the
Related Information
Clock Control Block (ALTCLKCTRL) Megafunction User Guide
Provides more information about ALTCLKCTRL megafunction.
PCLK Control Block
To drive the HSSI horizontal PCLK control block, select the HSSI output or internal logic .
Figure 4-11: Horizontal PCLK Control Block for Cyclone V Devices
External PLL Clock Output Control Block
You can enable or disable the dedicated external clock output pins using the ALTCLKCTRL megafunction.
Clock Networks and PLLs in Cyclone V Devices
Send Feedback
CLKp
CLKn
Pin Pin
2
PLL Counter
Internal Logic
Outputs
Static Clock Select
Enable/
Disable
Internal
Logic
RCLK
clkena
signal. The inputs from the clock pins feed the
CLKSELECT[0..1]
HSSI Output
Horizontal PCLK
The CLKn pin is not a dedicated
clock input when used as a
single-ended PLL clock input. The
CLKn pin can drive the PLL using
the RCLK.
When the device is in user mode,
you can only set the clock select
signals through a configuration file
(.sof or .pof); they cannot be
controlled dynamically.
signals for the GCLK and RCLK network multiplexers
inclk[2..3]
Internal Logic
Static Clock Select
4-13
PCLK Control Block
inclk[0..1]
ports.
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