Altera Cyclone V Device Handbook page 308

CV-53001
2013.05.06
Counter
L (PD)
Channel PLL as CDR PLL
When configured as a receiver CDR, each channel PLL independently recovers the clock from the incoming
serial data. The serial and parallel recovered clocks are used to clock the receiver PMA and PCS blocks.
The CDR supports the full range of data rates. The voltage-controlled oscillator (VCO) operates at half rate.
The L-counter dividers (PD) after the VCO extend the CDR data rate range. The Quartus II software
automatically selects these settings.
The CDR operates in either lock-to-reference (LTR) or lock-to-data (LTD) mode. In LTR mode, the CDR
tracks the input reference clock. In LTD mode, the CDR tracks the incoming serial data.
The time needed for the CDR PLL to lock to data depends on the transition density and jitter of the incoming
serial data and the PPM difference between the receiver input reference clock and the upstream transmitter
reference clock. You must hold the receiver PCS in reset until the CDR PLL locks to data and produces a
stable recovered clock.
After the receiver power up and reset cycle, you must keep the CDR in LTR mode until the CDR locks to
the input reference clock. When locked to the input reference clock, the CDR output clock is trained to the
configured data rate. The CDR then switches to LTD mode to recover the clock from the incoming data.
The LTR/LTD controller controls the switch between the LTR and LTD modes.
Figure 1-17: Channel PLL Block Diagram
From Signal
Detect Circuit (1)
Manual Lock
Controls
rx_serial_data
Notes:
1. Applicable in a PCIe configuration and custom mode configuration, for example SATA/SAS.
2. Applicable when configured as a CDR PLL.
3. Applicable when configured as a CMU PLL.
Transceiver Architecture in Cyclone V Devices
Send Feedback
VCO post-scale counter to divide the VCO output frequency
by the L factor in the LTD loop
Channel PLL
LTR/LTD
Controller
Phase
Detector
(PD)
Phase
refclk
/N
Frequency
Detector
(PFD)
Description
Down
LTD Mode
Up
Voltage
Charge Pump
Controlled
&
Oscilator
Loop Filter
(VCO)
Up
Down
Detect
LTR Mode
Channel PLL as CDR PLL
Values
1, 2, 4, 8
rx_is_lockedtodata
Recovered Clock
/L(PD)
to Deserializer (2)
/L(PFD) Serial Clock (3)
Lock
rx_is_lockedtoref
/M
1-21
Altera Corporation