Altera Cyclone V Device Handbook page 420

Hide thumbs Also See for Cyclone V:
Table of Contents

Advertisement

CV-53005
2013.05.06
Data Configuration
Double-width
In all the supported configuration options of the channel, the transmitter bit-slip function is optional,
where:
• The blocks shown as "Disabled" are not used but incur latency.
• The blocks shown as "Bypassed" are not used and do not incur any latency.
• The transmitter bit-slip is disabled.
Figure 5-3: Configuration Options for Custom Single-Width Mode (8-bit PMA PCS Interface Width)
Transceiver Custom Configurations in Cyclone V Devices
Send Feedback
PCS-FPGA Fabric Interface Width
PMA-PCS
Interface
8B/10B
Width
Enabled
16
16
20
32
Word Aligner (Pattern Length)
8B/10B Encoder/Decoder
Rate Match FIFO
Byte SERDES
FPGA Fabric–Transceiver
Interface Width
Data Rate (Gbps)
Custom Configuration Channel Options
Maximum Data
Rate for GX
8B/10B
and SX (Mbps)
Disabled
16
2,621.44
32
3,125
20
3,125
40
3,125
Manual Alignment
or Bit-Slip
Disabled
Disabled
Disabled
Enabled
8-Bit
16-Bit
1.5
3.0
5-3
Maximum Data Rate for GT
and ST (Mbps)
2,621.44
5,000
3,276.8
5,000
Altera Corporation

Advertisement

Table of Contents
loading

Table of Contents