Lvds Serdes Circuitry - Altera Cyclone V Device Handbook

5-54

LVDS SERDES Circuitry

Figure 5-32: High-Speed Differential I/O Locations in Cyclone V SE A2, A4, A5, and A6 Devices
Figure 5-33: High-Speed Differential I/O Locations in Cyclone V SX C2, C4, C5, and C6 Devices, and Cyclone V
ST D5 and D6 Devices
Related Information
PLLs and Clocking
I/O design guidelines related to PLLs and clocking.
Guideline: Use PLLs in Integer PLL Mode for LVDS
LVDS SERDES Circuitry
The following figure shows a transmitter and receiver block diagram for the LVDS SERDES circuitry with
the interface signals of the transmitter and receiver data paths.
Altera Corporation
General Purpose I/O and High-Speed
LVDS I/O with SERDES
Fractional PLL
HPS I/O
General Purpose I/O and High-Speed
LVDS I/O with SERDES
Fractional PLL
HPS I/O
Transceiver Block
on page 5-12
HPS Core
FPGA Fabric
(Logic Elements, DSP,
Embedded Memory,
Clock Networks)
HPS Core
FPGA Fabric
(Logic Elements, DSP,
Embedded Memory,
Clock Networks)
on page 5-12
I/O Features in Cyclone V Devices
CV-52005
2014.01.10
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