Altera Cyclone V Device Handbook page 86

CV-52004
2014.01.10
Figure 4-29: ZDB Mode in Cyclone V PLLs
inclk
Figure 4-30: Example of Phase Relationship Between the PLL Clocks in ZDB Mode
Related Information
PLL External Clock I/O Pins
Provides more information about PLL clock outputs.
External Feedback Mode
In EFB mode, the output of the
board) and becomes part of the feedback loop.
Clock Networks and PLLs in Cyclone V Devices
Send Feedback
÷N PFD CP/LF
Clock at the Input Pin
The internal PLL clock
output can lead or lag
Register Clock Port
the external PLL clock
outputs.
on page 4-23
counter (
M
C0
C1
C2
C3
Multiplexer
C4
10 2
VCO
C5
C6
C7
C8
M
Phase Aligned
PLL Reference
PLL Clock at the
Dedicated PLL
Clock Outputs
feeds back to the PLL
fbout)
External Feedback Mode
fbout
EXTCLKOUT[0]
fbin
EXTCLKOUT[1]
input (using a trace on the
fbin
4-29
FPLL_<#>_FB
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