Serial Digital Interface Transceiver Datapath; Serial Data Converter (Sdc) Jesd204 - Altera Cyclone V Device Handbook

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Serial Digital Interface Transceiver Datapath

Serial Digital Interface Transceiver Datapath
Figure 4-25: SDI Mode Transceiver Datapath
FPGA Fabric
tx_coreclk
FPGA
Fabric–Transceiver
Interface Clock
rx_coreclk
Transmitter Datapath
The transmitter datapath in the HD-SDI configuration with a 10-bit wide FPGA fabric-transceiver interface
consists of the transmitter phase compensation FIFO and the 10:1 serializer. In HD-SDI and 3G-SDI
configurations with 20-bit wide FPGA fabric-transceiver interface, the transmitter datapath also includes
the byte serializer.
Note: In SDI mode, the transmitter is purely a parallel-to-serial converter. You must implement the SDI
transmitter functions, such as the scrambling and cyclic redundancy check (CRC) code generation,
in the FPGA logic array.
Receiver Datapath
In the 10-bit channel width SDI configuration, the receiver datapath consists of the clock recovery unit
(CRU), 1:10 deserializer, word aligner in bit-slip mode, and receiver phase compensation FIFO. In the 20-
bit channel width SDI configuration, the receiver datapath also includes the byte deserializer.
Note: You must implement the SDI receiver functions, such as descrambling, framing, and CRC checker,
in the FPGA logic array.
Receiver Word Alignment and Framing
In SDI systems, the word aligner in the receiver datapath is not useful because the word alignment and
framing happen after descrambling. Altera recommends that you drive the rx_bitslip of the PHY
™
MegaWizard

Serial Data Converter (SDC) JESD204

The SDC (JESD204) protocol conforms to JESD204, a JEDEC standard that enables a high-speed serial
connection between analog-to-digital converters and logic devices using only a two-wire high-speed serial
Altera Corporation
TX Phase
Compensation
FIFO
wrclk rdclk
tx_clkout
RX Phase
Compensation
FIFO
rx_clkout
signal low to avoid having the word aligner insert bits in the received data stream.
Transmitter Channel PCS
Byte
Serializer
wrclk rdclk
/2
Low-Speed Parallel Clock
Receiver Channel PCS
Byte
Word
Deserializer
Aligner
/2
Parallel Recovered Clock
Transceiver Protocol Configurations in Cyclone V Devices
Transmitter Channel PMA
Serializer
High-Speed Serial Clock
Local Clock
Divider
Receiver Channel PMA
Deserializer CDR
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CV-53004
2013.10.17