Timer Introduction; Features Of The Timer; Timer Block Diagram And System Integration - Altera Cyclone V Device Handbook

2013.12.30
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The hard processor system (HPS) provides four, 32-bit, general-purpose timers connected to the level 4 (L4)
peripheral bus.
The timers optionally generate an interrupt when the 32-bit binary count-down timer reaches zero. The
timers are instances of the Synopsys
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Related Information
Cortex-A9 MPCore
The MPU subsystem provides additional timers. For more information about the timers in the MPU, refer
to the Cortex-A9 Microprocessor Unit Subsystem chapter.

Features of the Timer

• Supports interrupt generation
• Supports free-running mode
• Supports user-defined count mode

Timer Block Diagram and System Integration

Each timer includes a slave interface for control and status register (CSR) access, a register block, and a
programmable 32-bit down counter that generates interrupts on reaching zero. The timer operates on a
single clock domain driven by the clock manager.
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Timer Introduction

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APB Timers (DW_apb_timers) peripheral.
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