Emulated Lvds Buffers In Cyclone V Devices; Differential Transmitter In Cyclone V Devices; Transmitter Blocks - Altera Cyclone V Device Handbook

CV-52005
2014.01.10
Related Information
Guideline: Use PLLs in Integer PLL Mode for LVDS

Emulated LVDS Buffers in Cyclone V Devices

The Cyclone V device family supports emulated LVDS on all I/O banks:
You can use unutilized true LVDS input channels as emulated LVDS output buffers (eTX), which use
two single-ended output buffers with an external resistor network to support LVDS, mini-LVDS, and
RSDS I/O standards.
The emulated differential output buffers support tri-state capability.

Differential Transmitter in Cyclone V Devices

The Cyclone V transmitter contains dedicated circuitry to support high-speed differential signaling. The
differential transmitter buffers support the following features:
LVDS signaling that can drive out LVDS, mini-LVDS, and RSDS signals
Programmable V

Transmitter Blocks

The dedicated circuitry consists of a true differential buffer, a serializer, and fractional PLLs that you can
share between the transmitter and receiver. The serializer takes up to 10 bits wide parallel data from the
FPGA fabric, clocks it into the load registers, and serializes it using shift registers that are clocked by the
fractional PLL before sending the data to the differential buffer. The MSB of the parallel data is transmitted
first.
Note: To drive the LVDS channels, you must use the PLLs in integer PLL mode.
The following figure shows a block diagram of the transmitter. In SDR and DDR modes, the data width is
1 and 2 bits, respectively.
Figure 5-35: LVDS Transmitter
Related Information
Guideline: Use PLLs in Integer PLL Mode for LVDS
I/O Features in Cyclone V Devices
Send Feedback
and programmable pre-emphasis
OD
FPGA
Fabric
10 bits
10
tx_in
maximum
data width
tx_coreclock
(LVDS_LOAD_EN, diffioclk, tx_coreclock)
3
Fractional PLL
Emulated LVDS Buffers in Cyclone V Devices
on page 5-12
2
IOE IOE supports SDR, DDR, or non-registered datapath
Serializer
DIN DOUT
tx_inclock
on page 5-12
+ tx_out
–
LVDS Transmitter
LVDS Clock Domain
Altera Corporation
5-63