Pll Cascading; Pll External Clock I/O Pins - Altera Cyclone V Device Handbook

CV-52004
2014.01.10
Reduce the clock pins used in the FPGA by synthesizing multiple clock frequencies from a single reference
clock source
Compensate clock network delay
Zero delay buffering
Transmit clocking for transceivers

PLL Cascading

Cyclone V devices support two types of PLL cascading.
PLL-to-PLL Cascading
This cascading mode synthesizes a more precise output frequency than a single PLL in integer mode.
Cascading two PLLs in integer mode expands the effective range of the pre-scale counter,
counter,
M
Cyclone V devices only use
PLLs.
Altera recommends using a low bandwidth setting for the source (upstream) PLL and a high bandwidth
setting for destination (downstream) PLL.
Counter-Output-to-Counter-Output Cascading
This cascading mode synthesizes a lower frequency output than a single post-scale counter,
two counters expands the effective range of
C

PLL External Clock I/O Pins

All Cyclone V external clock outputs for corner fractional PLLs (that are not from the PLL strips) are dual-
purpose clock I/O pins. Two external clock output pins associated with each corner fractional PLL are
organized as one of the following combinations:
Two single-ended clock outputs
One differential clock output
Two single-ended clock outputs and one single-ended clock input in the I/O driver feedback for zero
delay buffer (ZDB) mode support
One single-ended clock output and one single-ended feedback input for single-ended external feedback
(EFB) mode support
One differential clock output and one differential feedback input for differential EFB support
Note: The external clock outputs support is dependent on the device density and package.
The following figure shows that any of the output counters (
the dedicated external clock outputs. Therefore, one counter or frequency can drive all output pins available
from a given PLL.
Clock Networks and PLLs in Cyclone V Devices
Send Feedback
.
adjpllin
input clock source for inter-cascading between fracturable fractional
counters.
C
C[0..8]
PLL Cascading
and the multiply
N
C
) or the counter on the PLLs can feed
M
Altera Corporation
4-23
. Cascading