Altera Cyclone V Device Handbook page 853

17-4
EMAC to RGMII Interface
EMAC Port
phy_txen_o
rst_clk_tx_n_o
clk_rx_i
phy_rxd_i
phy_rxdv_i
rst_clk_rx_n_o
phy_intf_sel_i[1:0]
clk_ref_i
Altera Corporation
In/Out Width
Out 1
Out 1
In 1
In 8
In 1
Out 1
In 2
In 1
Description
PHY Transmit Data Enable. This signal is
driven by the EMAC component. RGMII: This
signal is the control signal (rgmii_tctl) for the
transmit data, and is driven on both edges of
the clock. Synchronous to: clk_tx_i,
clk_tx_180_i
Transmit clock reset output.
Receive clock. Clock frequency is 125/25/2.5
MHz in 1 G/100 M/10 Mbps modes. It is
provided by the external PHY. All PHY signals
received by the EMAC are synchronous to this
clock.
PHY Receive Data. This is a bundle of eight
data signals received from the PHY. RGMII:
Bits [3:0] provide the RGMII receive data. The
data bus is sampled with both rising and falling
edges of the receive clock (clk_rx_i). The
validity of the data is qualified with phy_rxdv_i.
Synchronous to: clk_rx_i, clk_rx_180_i
PHY Receive Data Valid. This signal is driven
by PHY. RGMII: This is the receive control
signal used to qualify the data received on
phy_rxd. This signal is sampled on both edges
of the clock. Synchronous to: clk_rx_i,
clk_rx_180_i
Receive clock reset output.
PHY Interface Select: These pins select one of
the PHY interfaces of the EMAC. This signal
is sampled only during reset assertion and
ignored after that.
• 01: RGMII
• 00, 10, and 11: Invalid
This is the reference clock to the EMAC. The
clock is emac0_clk or emac1_clk supplied by
the clock manager. The system manager drives
the phy_intf_sel signal to control which clock
is used.
The clock rate is 250 MHz.
Ethernet Media Access Controller
cv_54017
2013.12.30
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