Altera Cyclone V Device Handbook page 663

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2013.12.30
Correction Capability, Sector Size, and Check Bit Size
Table 10-17: Correction Capability, Sector Size, and Check Bit Size
Correction
4
8
16
24
ECC Programming Modes
The NAND flash controller provides the following ECC programming modes that software uses to format
a page:
• Main Area Transfer Mode
• Spare Area Transfer Mode
• Main+Spare Area Transfer Mode
Related Information
• Main Area Transfer Mode
• Spare Area Transfer Mode
• Main+Spare Area Transfer Mode
Main Area Transfer Mode
In main area transfer mode, when ECC is enabled, the NAND flash controller inserts ECC check bits in the
data stream on writes and strips ECC check bits on reads. Software does not need to manage the ECC sectors
when writing a page. ECC checking is performed by the flash controller, so software simply transfers the
data.
If ECC is turned off, the NAND flash controller does not read or write ECC check bits.
Figure 10-2: Main Area Transfer Mode Programming Model for ECC
Spare Area Transfer Mode
The NAND flash controller does not introduce or interpret ECC check bits in spare area transfer mode, and
acts as pass through for data transfer.
Figure 10-3: Spare Area Transfer Mode Programming Model for ECC
NAND Flash Controller
Send Feedback
Correction Capability, Sector Size, and Check Bit Size
Sector Size in Bytes
512
512
512
1024
on page 10-25
on page 10-25
on page 10-26
Sector 0 Sector 1 Sector 2
Sector 3 ECC3
Check Bit Size in Bytes
8
14
26
46
Sector 3
Flags
10-25
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