Altera Cyclone V Device Handbook page 4

TOC-4
Cyclone V Device Handbook Volume 1: Device Interfaces and Integration
Types of Clock Networks................................................................................................................4-3
Clock Sources Per Quadrant..........................................................................................................4-7
Types of Clock Regions...................................................................................................................4-8
Clock Network Sources...................................................................................................................4-9
Clock Output Connections...........................................................................................................4-11
Clock Control Block......................................................................................................................4-11
Clock Power Down........................................................................................................................4-14
Clock Enable Signals......................................................................................................................4-14
Cyclone V PLLs..........................................................................................................................................4-16
PLL Physical Counters in Cyclone V Devices............................................................................4-16
PLL Locations in Cyclone V Devices..........................................................................................4-17
PLL Migration Guidelines ...........................................................................................................4-22
Fractional PLL Architecture.........................................................................................................4-22
PLL Cascading................................................................................................................................4-23
PLL External Clock I/O Pins........................................................................................................4-23
PLL Control Signals.......................................................................................................................4-24
Clock Feedback Modes..................................................................................................................4-25
Clock Multiplication and Division..............................................................................................4-31
Programmable Phase Shift............................................................................................................4-32
Programmable Duty Cycle...........................................................................................................4-32
Clock Switchover...........................................................................................................................4-32
PLL Reconfiguration and Dynamic Phase Shift........................................................................4-37
Document Revision History.....................................................................................................................4-38
I/O Features in Cyclone V Devices......................................................................5-1
I/O Resources Per Package for Cyclone V Devices.................................................................................5-1
I/O Vertical Migration for Cyclone V Devices........................................................................................5-4
Verifying Pin Migration Compatibility........................................................................................5-5
I/O Standards Support in Cyclone V Devices..........................................................................................5-5
I/O Standards Support for FPGA I/O in Cyclone V Devices....................................................5-5
I/O Standards Support for HPS I/O in Cyclone V Devices........................................................5-7
I/O Standards Voltage Levels in Cyclone V Devices...................................................................5-8
MultiVolt I/O Interface in Cyclone V Devices..........................................................................5-10
I/O Design Guidelines for Cyclone V Devices.......................................................................................5-11
Mixing Voltage-Referenced and Non-Voltage-Referenced I/O Standards...........................5-11
PLLs and Clocking.........................................................................................................................5-12
LVDS Interface with External PLL Mode...................................................................................5-15
Guideline: Use the Same V
Altera Corporation
for All I/O Banks in a Group...............................................5-17
CCPD