Altera Cyclone V Device Handbook page 169

5-72
Receiver Skew Margin for LVDS Mode
Figure 5-46: RSKM Equation
Conventions used for the equation:
RSKM—the timing margin between the receiver's clock input and the data input sampling window.
Time unit interval (TUI)—time period of the serial data.
SW—the period of time that the input data must be stable to ensure that data is successfully sampled by
the LVDS receiver. The SW is a device property and varies with device speed grade.
TCCS—the timing difference between the fastest and the slowest output edges, including t
and clock skew, across channels driven by the same PLL. The clock is included in the TCCS measurement.
You must calculate the RSKM value to decide whether the LVDS receiver can sample the data properly or
not, given the data rate and device. A positive RSKM value indicates that the LVDS receiver can sample the
data properly, whereas a negative RSKM indicates that it cannot sample the data properly.
The following figure shows the relationship between the RSKM, TCCS, and the SW of the receiver.
Figure 5-47: Differential High-Speed Timing Diagram and Timing Budget for LVDS Mode
Timing Diagram
External
Input Clock
Internal
Clock
Receiver
Input Data
Timing Budget
External
Clock
Internal
Clock
Synchronization
Transmitter
Output Data
Receiver
Input Data
Altera Corporation
TCCS
RSKM
t
SW
RSKM
TCCS
Time Unit Interval (TUI)
SW RSKM
(min) Internal t (max)
SW
Bit n Clock Bit n
Falling Edge
TUI
Clock Placement
RSKM
SW
CO
TCCS
TCCS
2
I/O Features in Cyclone V Devices
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CV-52005
2014.01.10
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