Clock Divider - Altera Cyclone V Device Handbook

1-24
fPLL as a Transmitter PLL
Figure 1-18: CMU PLL in Cyclone V Devices
From Signal
Detect Circuit
Manual Lock
Controls
rx_serial_data
refclk
The CMU PLL output serial clock, with a frequency that is half of the data rate, feeds the clock divider that
resides in the transmitter of the same transceiver channel. The CMU PLLs in channels 1 and 4 feed the x1
and x6 clock lines.
Related Information
Transceiver Clocking in Cyclone V Devices
fPLL as a Transmitter PLL
In addition to CMU PLL, the fPLL located adjacent to the transceiver banks are available for clocking the
transmitters for serial data rates up to 3.125 Gbps.
Related Information
Clock Networks and PLLs in Cyclone V Devices

Clock Divider

Each Cyclone V transmitter channel has a clock divider.
There are two types of clock dividers, depending on the channel location in a transceiver bank:
• Local clock divider—channels 0, 2, 3, and 5 provide serial and parallel clocks to the PMA
• Central clock divider—channels 1 and 4 can drive the x6 and xN clock lines
Altera Corporation
Channel PLL
LTR/LTD
Controller
Down
Phase
Detector
Up
(PD)
Phase
Up
/N
Frequency
Detector
Down
(PFD)
Voltage
Charge Pump
Controlled
+
Oscilator
Loop Filter
(VCO)
Lock
Detect
/M
Transceiver Architecture in Cyclone V Devices
rx_is_lockedtodata
Recovered Clock
/L(PD)
to Deserializer
/L(PFD) Serial Clock
pll_locked
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CV-53001
2013.05.06