Altera Cyclone V Device Handbook page 540

cv_54005
2013.12.30
Signal
WREADY
Table 5-12: HPS-to-FPGA Bridge Master Write Response Channel Signals
Signal
BID
BRESP
BVALID
BREADY
Table 5-13: HPS-to-FPGA Bridge Master Read Address Channel Signals
Signal
ARID
ARADDR
ARLEN
ARSIZE
ARBURST
ARLOCK
ARCACHE
ARPROT
ARVALID
ARREADY
Table 5-14: HPS-to-FPGA Bridge Master Read Data Channel Signals
Signal
RID
RDATA
RRESP
RLAST
HPS-FPGA AXI Bridges
Send Feedback
Width
1 bit
Width Direction
12 bits Input
2 bits Input
1 bit Input
1 bit Output
Width Direction
12 bits Output
30 bits Output
4 bits Output
3 bits Output
2 bits Output
2 bits Output
4 bits Output
3 bits Output
1 bit Output
1 bit Input
Width Direction
12 bits Input
32, 64, or 128 bits Input
2 bits Input
1 bit Input
Direction
Input Write data channel ready
Write response ID
Write response
Write response channel valid
Write response channel ready
Read address ID
Read address
Burst length
Burst size
Burst type
Lock type Valid values are 00 (normal access) and
01 (exclusive access)
Cache policy type
Protection type
Read address channel valid
Read address channel ready
Read ID
Read data
Read response
Read last data identifier
HPS-to-FPGA Bridge Master Signals
Description
Description
Description
Description
5-9
Altera Corporation