Altera Cyclone V Device Handbook page 970

cv_54020
2013.12.30
The number of burst transactions needed equals the block size divided by the number of data items per
burst:
Block transaction size/DMA burst length = 240/48 = 5
The number of burst transactions in the DMA block transfer is 5. But the watermark level, IC_DMA_TDLR,
is quite low. Therefore, the probability of transmit underflow is high where the I
to transmit data, but there is no data left in the transmit FIFO. This occurs because the DMA has not had
time to service the DMA request before the FIFO becomes empty.
• Case 2: IC_DMA_TDLR = 48 †
• Transmit FIFO watermark level = IC_DMA_TDLR = 48 †
• DMA burst length = FIFO_DEPTH - IC_DMA_TDLR = 16 †
2
• I C transmit FIFO_DEPTH = 64 †
• Block transaction size = 240 †
Figure 20-12: Transmit FIFO Watermark Level = 48
Number of burst transactions in block: †
Block transaction size/DMA burst length = 240/16 = 15 †
In this block transfer, there are 15 destination burst transactions in a DMA block transfer. But the watermark
level, IC_ DMA_TDLR, is high. Therefore, the probability of I
controller has plenty of time to service the destination burst transaction request before the I
FIFO becomes empty. †
Thus, the second case has a lower probability of underflow at the expense of more burst transactions per
block. This provides a potentially greater amount of bursts per block and worse bus utilization than the
former case. †
Therefore, the goal in choosing a watermark level is to minimize the number of transactions per block, while
at the same time keeping the probability of an underflow condition to an acceptable level. In practice, this
is a function of the ratio of the rate at which the I
to destination burst requests. †
Transmit FIFO Overflow
Setting the DMA burst length to a value greater than the watermark level that triggers the DMA request
might cause overflow when there is not enough space in the transmit FIFO to service the destination burst
request. Therefore, the following equation must be adhered to in order to avoid overflow: †
DMA burst length <= FIFO_DEPTH - IC_DMA_TDLR
I2C Controller
Send Feedback
Transmit
FIFO Buffer
FIFO_DEPTH = 64
Transmit FIFO
Watermark Level
Data Out
Empty
FIFO_DEPTH - IC_DMA_TDLR = 16
Full
IC_DMA_TDLR = 48
2
C transmit underflow is low because the DMA
2
C transmits data to the rate at which the DMA can respond
Transmit FIFO Overflow
2
C serial transmit line needs
Data In
DMA
Controller
2
C transmit
Altera Corporation
20-19