Altera Cyclone V Device Handbook page 100

CV-52005
2014.01.10
Table 5-5: Package Plan for Cyclone V SX Devices
The HPS I/O counts are the number of I/Os in the HPS and does not correlate with the number of HPS-specific I/O
pins in the FPGA. Each HPS-specific pin in the FPGA may be mapped to several HPS I/Os.
Member Code
C2
C4
C5
C6
Table 5-6: Package Plan for Cyclone V ST Devices
The HPS I/O counts are the number of I/Os in the HPS and does not correlate with the number of HPS-specific I/O
pins in the FPGA. Each HPS-specific pin in the FPGA may be mapped to several HPS I/Os.
Member Code
D5
D6
For more information about each device variant, refer to the device overview.
Related Information
Cyclone V Device Overview
I/O Features in Cyclone V Devices
Send Feedback
U672
FPGA GPIO HPS I/O
145 181
145 181
145 181
145 181
FPGA GPIO
288
288
I/O Resources Per Package for Cyclone V Devices
XCVR FPGA GPIO
6 —
6 —
6 288
6 288
F896
HPS I/O
181
181
F896
HPS I/O XCVR
— —
— —
181 9
181 9
XCVR
9
9
Altera Corporation
5-3