Guidelines For Dynamic Reconfiguration If Transmitter Duty Cycle Distortion Calibration Is Required During Device Operation; Transceiver Blocks Affected By The Reset And Powerdown Signals - Altera Cyclone V Device Handbook

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Guidelines for Dynamic Reconfiguration if Transmitter Duty Cycle Distortion Calibration is Required during
Device Operation
2. Repeat the sequence as needed after dynamic reconfiguration is complete, which is indicated by
deassertion of the reconfig_busy, tx_cal_busy, rx_cal_busy signals.
Guidelines for Dynamic Reconfiguration if Transmitter Duty Cycle Distortion Calibration
is Required during Device Operation
If transmitter duty cycle distortion calibration is required during device operation, ensure the general
guidelines for transceiver dynamic reconfiguration are followed. Additionally, use the following
recommendations:
1. Do not connect tx_cal_busy to the transceiver Reset Controller IP.
2. Disable the embedded reset controller and use an external reset controller.
Note: If channel reconfiguration is required before TX DCD calibration, ensure the following:
• The TX PLL, TX channel, and Transceiver Reconfiguration Controller blocks must not be in
the reset state during TX DCD calibration. Ensure the following signals are not asserted during
TX DCD calibration:
• pll_powerdown
• tx_digitalreset
• tx_analogreset
• mgmt_rst_reset
Repeat the reset sequence when TX DCD calibration is complete.

Transceiver Blocks Affected by the Reset and Powerdown Signals

The following table lists blocks that are affected by specific reset and powerdown signals
Table 3-6: Transceiver Blocks Affected
Transceiver Block
CMU PLL
Receiver Word Aligner
Receiver Deskew FIFO
Receiver Rate Match FIFO
Receiver 8B/10B Decoder
Receiver Byte Deserializer
Receiver Byte Ordering
Altera Corporation
pll_ rx_digital-
powerdown reset
PLL
Yes —
Receiver Standard PCS
— Yes
— Yes
— Yes
— Yes
— Yes
— Yes
rx_analogreset tx_digitalreset
— —
— —
— —
— —
— —
— —
— —
Transceiver Reset Control in Cyclone V Devices
CV-53003
2013.05.06
tx_analogreset
—
—
—
—
—
—
—
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