Hps Peripheral Region Address Map - Altera Cyclone V Device Handbook

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HPS Peripheral Region Address Map

Table 1-4: L3 Address Space Regions
Identifier
L3SDRAM
L3LOWOCRAM
L3ACP
Related Information
• Interconnect
For information about the L3 GPV remap control register bits, refer to the Interconnect chapter.
• Cortex-A9 Microprocessor Unit Subsystem
For more information about the ACP ID mapper, refer to the Cortex-A9 Microprocessor Unit Subsystem
chapter.
HPS Peripheral Region Address Map
Table 1-5 lists the slave identifier, slave title, base address, and size of each slave in the peripheral region.
The Slave Identifier column lists the names used in the HPS register map. The Slave Title column contains
the module name for modules with only one slave and module names plus a suffix for modules with more
than one slave.
Table 1-5: Peripheral Region Address Map
Slave Identifier
STM
DAP
LWFPGASLAVES
LWHPS2FPGAREGS
HPS2FPGAREGS
FPGA2HPSREGS
EMAC0
EMAC1
SDMMC
Altera Corporation
Region Name
SDRAM
window
On-chip RAM
when present
ACP window
on page 4-1
Slave Title
STM
DAP
FPGA slaves accessed with
lightweight FPGA-to-HPS
AXI bridge
Lightweight FPGA-to-HPS
AXI bridge GPV
HPS-to-FPGA AXI bridge
GPV
FPGA-to-HPS AXI bridge
GPV
EMAC0
EMAC1
SD/MMC
Base Address
0x00000000
0x00000000
0x80000000
on page 6-1
Base Address
0xFC000000
0xFF000000
0xFF200000
0xFF400000
0xFF500000
0xFF600000
0xFF700000
0xFF702000
0xFF704000
Introduction to Cyclone V Hard Processor System (HPS)
Size
2 GB
64 KB
1 GB
Size
48 MB
2 MB
2 MB
1 MB
1 MB
1 MB
8 KB
8 KB
4 KB
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2013.12.30