Altera Cyclone V Device Handbook page 334

CV-53001
2013.05.06
Figure 1-32: Byte Ordering Operation Example in Single-Width Mode
An example of a byte ordering operation in single-width mode (8-bit PMA-PCS interface width) where A
is the predefined byte ordering pattern and P is the predefined pad pattern.
datain[15:8] D2
D1
datain[7:0]
Byte Ordering in Double-Width Mode
Byte ordering is supported only when you enable the byte deserializer.
Table 1-29: Byte Ordering Operation in Double-Width Mode
PMA PCS Interface Width
16 bits
20 bits
Figure 1-33: Byte Ordering Operation Example in Double-Width Mode
An example of a byte ordering operation in double-width mode (16-bit PMA-PCS interface width) where
A1A2 is the predefined byte ordering pattern and P is the predefined pad pattern.
datain[31:16]
D2D3
(MSByte)
datain[15:0]
D0D1
(LSByte)
Word Aligner-Based Ordering Mode
In word aligner-based ordering mode, the byte ordering operation is controlled by the word aligner
synchronization status signal, rx_syncstatus.
After a rising edge on the rx_syncstatus signal, byte ordering looks for the byte ordering pattern in the
byte-deserialized data.
(4)
The MSB of the 9-bit pattern represents the 1-bit control identifier of the 8B/10B-decoded data. The lower 8
bits represent the 8-bit decoded code.
(5)
The 18-bit pattern consists of two sets of 9-bit patterns, individually represented as in the previous note.
Transceiver Architecture in Cyclone V Devices
Send Feedback
Transmitter Channel
D3 D5
Byte
Serializer
A D4
FPGA
Fabric Transceiver
Interface Width
32 bits
32 bits
40 bits
Transmitter Channel
D4D5 D8D9
Byte
Serializer
B1B2 D6D7
Byte Ordering in Double-Width Mode
Receiver
D1 A D4
Byte
Deserializer
XX D2 D3
8B/10B Decoder Byte Ordering
Pattern Length
Disabled 8 or 16 bits
(4)
Enabled 9 or 18 bits
Disabled 10 or 20 bits
Receiver
D0D1 A1A2 D6D7
Byte
Deserializer
xxxx D2D3 D4D5
D1 P D3 D5
Byte
Ordering
XX D2 A D4
Pad Pattern Length
8 bits
(5) (4)
9 bits
10 bits
D0D1 PP D4D5 D8D9
Byte
Ordering
xxxx D2D3 A1A2 D6D7
Altera Corporation
1-47
dataout[15:8]
dataout[7:0]
dataout[31:16]
(MSByte)
dataout[15:0]
(LSByte)