Guideline: Using Dq/Dqs Pins; Dq/Dqs Bus Mode Pins For Cyclone V Devices - Altera Cyclone V Device Handbook

CV-52006
2014.01.10
Related Information
Planning Pin and FPGA Resources chapter, External Memory Interface Handbook
Provides more information about which pins to use for memory clock pins and pin location requirements.

Guideline: Using DQ/DQS Pins

The following list provides guidelines on using the DQ/DQS pins:
The devices support DQ and DQS signals with DQ bus modes of x8 or x16. Cyclone V devices do not
support the x4 bus mode.
You can use the DQSn pins that are not used for clocking as DQ pins.
If you do not use the DQ/DQS pins for memory interfacing, you can use these pins as user I/Os. However,
unused HPS DQ/DQS pins on the Cyclone V SX and ST devices cannot be used as user I/Os.
Some specific DQ pins can also be used as RZQ pins. If you need extra RZQ pins, you can use these the
DQ pins as RZQ pins instead.
Note: For the x8 or x16 DQ/DQS groups whose members are used as RZQ pins, Altera recommends that
you assign the DQ and DQS pins manually. Otherwise, the Quartus II software might not be able to
place the DQ and DQS pins, resulting in a "no-fit" error.
Reading the Pin Table
For the maximum number of DQ pins and the exact number per group for a particular Cyclone V device,
refer to the relevant device pin table.
In the pin tables, the DQS and DQSn pins denote the differential data strobe/clock pin pairs. The DQS and
DQSn pins are listed respectively in the Cyclone V pin tables as
grouping number and Y indicates whether the group is located on the top (T), bottom (B), left (L), or right
(R) side of the device.
Note: The F484 package of the Cyclone V E A9, GX C9, and GT D9 devices can only support a 24 bit hard
memory controller on the top side using the
F484 package pin tables of these devices list
columns, you cannot use these pin assignments for the hard memory controller.
Related Information
Hard Memory Controller Width for Cyclone V E
Hard Memory Controller Width for Cyclone V GX
Hard Memory Controller Width for Cyclone V GT
Cyclone V Device Pin-Out Files
Download the relevant pin tables from this web page.

DQ/DQS Bus Mode Pins for Cyclone V Devices

The following table lists the pin support per DQ/DQS bus mode, including the DQS and DQSn pin pairs.
The maximum number of data pins per group listed in the table may vary according to the following
conditions:
Single-ended DQS signaling—the maximum number of DQ pins includes data mask connected to the
DQS bus network.
External Memory Interfaces in Cyclone V Devices
Send Feedback
Guideline: Using DQ/DQS Pins
and
DQSXY DQSnXY
to pin assignments. Even though the
T_DQ_0 T_DQ_23
to in the "HMC Pin Assignment"
T_DQ_32 T_DQ_39
on page 6-35
on page 6-36
on page 6-37
6-3
. X indicates the DQ/DQS
Altera Corporation