Altera Cyclone V Device Handbook page 481

cv_54002
2013.12.30
Figure 2-3: Main Clock Group Divide and Gating
Main
C0
PLL
C1
C2
C3
C4
C5
periph_base_clk (from Peripheral PLL C4)
The clocks derived from main PLL C0-C2 outputs are hardware-managed, meaning hardware ensures that
a clean transition occurs, and can have the following control values changed dynamically by software write
accesses to the control registers:
• PLL bypass
• PLL numerator, denominator, and counters
• External dividers
For these registers, hardware detects that the write has occurred and performs the correct sequence to ensure
that a glitch-free transition to the new clock value occurs. These clocks can pause during the transition.
Clock Manager
Send Feedback
mpu_base_clk
main_base_clk
dbg_base_clk
main_qspi_base_clk
main_nand_sdmmc_base_clk
cfg_h2f_user0_base_clk
Divide
by 4
Divide
by 2
Clock Gate
Clock Gate
Clock Gate
Divide
by 1 or 2
To Flash
Controller
Clocks
Divide by
1, 2, or 4
Divide by
1, 2, 4, 8, or 16
Main Clock Group
Clock Gate
Clock Gate
Divide
by 1 or 2
Divide by
Clock Gate
1, 2, 4, 8, or 16
Divide by
Clock Gate
1, 2, 4, 8, or 16
Clock Gate
Divide
Clock Gate
by 2 or 4
Clock Gate
Clock Gate
Clock Gate
Clock Gate
Altera Corporation
2-7
mpu_periph_clk
mpu_l2_ram_clk
mpu_clk
l4_main_clk
l3_main_clk
l3_mp_clk
l3_sp_clk
l4_mp_clk
l4_sp_clk
dbg_at_clk
dbg_clk
dbg_trace_clk
dbg_timer_clk
cfg_clk
h2f_user0_clock