Pin Directions; Gpio Interface Programming Model; Gpio Interface Address Map And Register Definitions - Altera Cyclone V Device Handbook

cv_54022
2013.12.30
Figure 22-2: Debounce Timing With Asychronous Reset Flip-Flops
gpio_db_clk
gpio_ext_porta
gpio_intr_in
Note: Enabling the debounce circuitry increases interrupt latency by two clock cycles of the debounce clock.

Pin Directions

The pins GPIO0 through GPIO70 can be configured to be either input or output signals. The pins HLGPI0
through HLGPI13 share pins with the HPS DDR controller and are input-only signals.

GPIO Interface Programming Model

Debounce capability for each of the input signals on port A can be enabled or disabled under software control
by setting the corresponding bits in the gpio_debounce register accordingly. The debounce clock must
be stable and operational before the debounce capability is enabled.
Under software control, the direction of the external I/O pad is controlled by a write to the
gpio_swportx_ddr register. When configured as input mode, reading gpio_ext_porta would read
the values on the signal of the external I/O pad. When configured as output mode, the data written to the
gpio_swporta_dr register drives the output buffer of the I/O pad. The same pins are shared for both
input and output modes, so they cannot be configured as input and output modes at the same time. †

GPIO Interface Address Map and Register Definitions

Note: The address map and register definitions reside in the hps.html file that accompanies this handbook
volume. Click the link to open the file.
To view the module description and base address, scroll to and click the link for any of the following module
instances:
• gpio0
• gpio1
• gpio2
To then view the register and field descriptions, scroll to and click the register names. The register addresses
are offsets relative to the base address of each module instance.
General-Purpose I/O Interface
Send Feedback
The signal is not registered
because it does not meet the
debounce clock's 2-cycle
requirement.
Because the signal is
registered, it generates
the interrupt signal.
This signal is registered because
it meets the debounce clock's 2-cycle
requirements
22-3
Pin Directions
Interrupt
Cleared
Altera Corporation