Generating A Preloader Image For Hps With Emif; Creating A Qsys Project In Preparation For Generating A Preloader Image; Creating A Top-Level File And Adding Constraints - Altera Cyclone V Device Handbook

cv_54008
2013.12.30
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// Deassert reset
<base name>.hps.fpga_interfaces.h2f_reset_inst.reset_deassert();
end

Generating a Preloader Image for HPS with EMIF

To generate a Preloader image for an HPS-based external memory interface, you must complete the following
tasks:
• Create a Qsys project.
• Create a top-level file and add constraints.
• Create a Preloader BSP file.
• Create a Preloader image.
The following topics provide procedures for each of the above tasks.

Creating a Qsys Project in Preparation for Generating a Preloader Image

This topic describes creating a Qsys project in preparation for generating a Preloader image.
1. On the Tools menu in the Quartus II software, click Qsys.
2. Under Component library, expand Embedded Processor System, select Hard Processor System and
click Add.
3. Specify parameters for the FPGA Interfaces, Peripheral Pin Multiplexing, and HPS Clocks, based on
your design requirements.
4. On the SDRAM tab, select the SDRAM protocol for your interface.
5. Populate the necessary parameter fields on the PHY Settings, Memory Parameters, Memory Timing,
and Board Settings tabs.
6. Add other Qsys components in your Qsys design and make the appropriate bus connections.
7. Save the Qsys project.
8. Click Generate on the Generation tab, to generate the Qsys design.

Creating a Top-Level File and Adding Constraints

This topic describes adding your Qsys system to your top-level design and adding constraints to your design.
1. Add your Qsys system to your top-level design.
2. Add the Quartus II IP files (
3. Perform analysis and synthesis on your design.
4. Constrain your EMIF design by running the <variation_name>
script.
5. Add other necessary constraints such as timing constraints, location assignments, and pin I/O standard
assignments for your design.
6. Compile your design to generate an SRAM object file (
creating a preloader image.
Note:
SDRAM Controller Subsystem
Send Feedback
) generated in step 2, to your Quartus II project.
.qip
You must regenerate the hardware handoff files whenever the HPS configuration changes; for
example, due to changes in Peripheral Pin Multiplexing or I/O standard for HPS pins.
Generating a Preloader Image for HPS with EMIF
_p0_pin_assignments.tcl
) and the hardware handoff files necessary for
.sof
8-25
pin constraints
Altera Corporation