Differential I/O Bit Position - Altera Cyclone V Device Handbook

5-70

Differential I/O Bit Position

Figure 5-44: Bit Orientation in the Quartus II Software
This figure shows the data bit orientation of the x10 mode.
Differential I/O Bit Position
Data synchronization is necessary for successful data transmission at high frequencies.
The following figure shows the data bit orientation for a channel operation and is based on the following
conditions:
The serialization factor is equal to the clock multiplication factor.
The phase alignment uses edge alignment.
The operation is implemented in hard SERDES.
Figure 5-45: Bit-Order and Word Boundary for One Differential Channel
Transmitter Channel Operation (x8 Mode)
tx_outclock
tx_out
Receiver Channel Operation (x8 Mode)
rx_inclock
rx_in
rx_outclock
rx_out [7..0]
For other serialization factors, use the Quartus II software tools to find the bit position within the word.
Differential Bit Naming Conventions
The following table lists the conventions for differential bit naming for 18 differential channels. The MSB
and LSB positions increase with the number of channels used in a system.
Table 5-42: Differential Bit Naming
This table lists the conventions for differential bit naming for 18 differential channels, and the bit positions after
deserialization.
Receiver Channel Data Number
1
2
3
4
Altera Corporation
incloc k/outcloc k
MSB
data in
9
Previous Cycle Current Cycle
7 6 5
X X X X X X X X
MSB
7 6 5 4 3 2 1 0
X X
X X X X X X X X X X X X X X X X
10 LVDS Bits
8 7 6 5 4 3
Next Cycle
4 3 2 1 0
X X X X X X
LSB
X X X X X X X X X X
X X X X 7 6 5 4
Note: These waveforms are only functional waveforms and do not convey timing information
Internal 8-Bit Parallel Data
MSB Position
7
15
23
31
LSB
2 1 0
X X
X X X X X X X X X X
3 2 1 0 X X X X
LSB Position
0
8
16
24
I/O Features in Cyclone V Devices
CV-52005
2014.01.10
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